In semiconductor manufacture, extremely small electronic devices are formed in separate dies on a thin, flat semiconductor wafer. The separate dies or chips are then separated from the wafer and packaged to form different types of IC chips. In general, various materials which are either conductive, insulating, or semiconducting are utilized to form the electronic devices. These materials are patterned, doped with impurities, or deposited in layers by various processes to form the integrated circuits. A completed circuit device is referred to as an integrated circuit (IC).
One process that is utilized in the fabrication of integrated circuits (ICs) is referred to as chemical mechanical planarization (CMP). In general, chemical mechanical planarization (CMP) involves holding or rotating a thin, flat wafer of semiconductor material on which ICs have been formed en masse against a wetted polishing surface. A chemical slurry containing a polishing agent such as alumina or silica is typically utilized as the abrasive medium. Additionally, the chemical slurry may contain chemical etchants for etching various surfaces of the wafer.
In general, a semiconductor wafer may be subjected to chemical mechanical planarization (CMP) to planarize the wafer and to remove topography. A (CMP) process may also be used to remove different layers of material and various surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. The (CMP) process thus improves the quality and reliability of the integrated circuits (ICs) formed on the wafer.
In the chemical mechanical planarization (CMP) process, a rotating polishing head or wafer carrier, is typically utilized to hold the wafer under controlled pressure against a rotating polishing platen. Other process parameters such as time, temperature, and the composition and flow rate of the chemical slurry are also closely controlled. The polishing platen is typically covered with a relatively soft, pad material such as blown polyurethane. The chemical slurry is dispensed onto the polishing platen and is selected to provide an abrasive medium and chemical activity for the etching.
Such apparatus for polishing thin, flat semiconductor wafers are well known in the art. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh, for instance, disclose such apparatus. Another such apparatus is manufactured by Westech Engineering and designated as a Model 372 Polisher.
A particular problem encountered during a chemical mechanical planarization (CMP) process is in the control of the various process parameters to achieve the desired wafer characteristics. It may be desirable for instance, to achieve a particular surface smoothness or roughness or to planarize the wafer to a desired planar endpoint. As an example, it may be useful to remove a thickness of oxide material which has been deposited onto a substrate on which a variety of integrated circuit devices have been formed. In removing or planarizing this oxide, it may be necessary to remove the oxide to the top of the various integrated circuit devices without removing any portion of a device.
In the past, it has not been possible to monitor the characteristics of the wafer during the (CMP) process. The surface characteristics and planar endpoint of the planarized wafer surface have typically been detected by mechanically removing the semiconductor wafer from the (CMP) apparatus and physically examining the semiconductor wafer using instruments and techniques which ascertain dimensional and planar characteristics. Measurement instruments include surface profilometers, ellipsometers, and quartz crystal oscillators. If the semiconductor wafer does not meet specifications, it must be loaded back into the (CMP) apparatus and planarized again. This is a time consuming and labor intensive procedure. In addition, an excess of material may have been removed from the semiconductor wafer rendering the part as unusable. There is therefore a need in the art for a process for monitoring the characteristics of a semiconductor wafer during the (CMP) process in order to insure the uniformity of the (CMP) process with respect to a single wafer and from wafer to wafer.
One prior art patent, U.S. Pat. No. 5,036,015, to Sandhu et al, which is assigned to the assignee of the present application, discloses an in-situ process for detecting a planar endpoint during the chemical mechanical planarization (CMP) process. In this process a change of friction between the wafer surface and polishing platen are sensed by measuring a load change on the drive motors for the chemical mechanical planarization apparatus. A change of friction may occur for example at the planar endpoint which separates different film layers on a wafer. While this process is effective for determining a planar endpoint on a wafer, it cannot be used to effect a continuous real time evaluation of the wafer in order to control the parameters of the chemical mechanical planarization (CMP) process.
One technique that has recently been adapted in semiconductor manufacture for controlling some fabrication processes is known as thermal imaging. In general, thermal imaging involves the remote sensing of temperature across the wafer using techniques such as pyrometry, fluoroptic thermometry, and laser interferometric thermometry. The technical article of reference [1] discloses a method of thermal imaging using an infrared TV camera for measuring the spatial temperature variation across the wafer. This information is then used to control the plasma etching process in real time.
The present invention is directed to a novel method and apparatus for controlling a semiconductor chemical mechanical planarization (CMP) process in real time by thermal imaging of the semiconductor wafer during the (CMP) process. This process is especially useful for insuring the uniformity of the (CMP) process with respect to a wafer.